<?xml version="1.0" encoding="utf-8"?><feed xmlns="http://www.w3.org/2005/Atom" ><generator uri="https://jekyllrb.com/" version="3.10.0">Jekyll</generator><link href="https://xiangui33423.github.io/yaowentao/feed.xml" rel="self" type="application/atom+xml" /><link href="https://xiangui33423.github.io/yaowentao/" rel="alternate" type="text/html" /><updated>2026-07-18T04:03:07+00:00</updated><id>https://xiangui33423.github.io/yaowentao/feed.xml</id><title type="html">wentao yao</title><subtitle>Academic portfolio of wentao yao, focused on CXL memory pooling, memory congestion, quantum computing compilation, and computer systems.</subtitle><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><entry><title type="html">A Brief Survey of Memory Bank Parallelism</title><link href="https://xiangui33423.github.io/yaowentao/blog/survey/memory-bank-parallelism/" rel="alternate" type="text/html" title="A Brief Survey of Memory Bank Parallelism" /><published>2026-05-21T00:00:00+00:00</published><updated>2026-05-21T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/survey/memory-bank-parallelism-survey</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/survey/memory-bank-parallelism/"><![CDATA[<p>This survey note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/2034621842829342353">A Brief Survey of Memory Bank Parallelism</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Surveys" /><category term="Memory Bank Parallelism" /><category term="Memory Systems" /><category term="DRAM" /><summary type="html"><![CDATA[A short survey note on Memory Bank Parallelism, covering the basic idea of bank-level parallelism and its performance impact in memory systems.]]></summary></entry><entry><title type="html">CXL Memory Interleaving and Address Mapping</title><link href="https://xiangui33423.github.io/yaowentao/blog/thoughts/cxl-interleave-address-mapping/" rel="alternate" type="text/html" title="CXL Memory Interleaving and Address Mapping" /><published>2026-01-29T00:00:00+00:00</published><updated>2026-01-29T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/thoughts/cxl-interleave-address-mapping-thought</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/thoughts/cxl-interleave-address-mapping/"><![CDATA[<p>This short note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/1976383570252691441">CXL Memory Interleaving and Address Mapping</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Notes" /><category term="CXL" /><category term="Memory Systems" /><category term="Address Mapping" /><summary type="html"><![CDATA[A short note on CXL memory interleaving and the address-mapping mechanisms behind it.]]></summary></entry><entry><title type="html">Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011</title><link href="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-1/" rel="alternate" type="text/html" title="Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011" /><published>2025-12-30T00:00:00+00:00</published><updated>2025-12-30T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/paper-reading/paper-reading-note-1</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-1/"><![CDATA[<p>This paper reading note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/1989353698451817771">Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Paper Reading" /><category term="Paper Reading" /><category term="Memory Systems" /><category term="Memory Channel Partitioning" /><summary type="html"><![CDATA[A paper reading note on application-aware memory channel partitioning for reducing memory interference in multicore systems.]]></summary></entry><entry><title type="html">Understanding Computer-System Performance Tradeoffs Through the Roofline Model</title><link href="https://xiangui33423.github.io/yaowentao/blog/thoughts/roofline-performance-tradeoff/" rel="alternate" type="text/html" title="Understanding Computer-System Performance Tradeoffs Through the Roofline Model" /><published>2025-11-24T00:00:00+00:00</published><updated>2025-11-24T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/thoughts/roofline-performance-thought</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/thoughts/roofline-performance-tradeoff/"><![CDATA[<p>This short note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/1994045427176208079">Understanding Computer-System Performance Tradeoffs Through the Roofline Model</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Notes" /><category term="Roofline" /><category term="Computer Systems" /><category term="Performance Analysis" /><summary type="html"><![CDATA[A short note on using the Roofline model to reason about performance bottlenecks and design tradeoffs in computer systems.]]></summary></entry><entry><title type="html">CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025</title><link href="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-2/" rel="alternate" type="text/html" title="CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025" /><published>2025-10-22T00:00:00+00:00</published><updated>2025-10-22T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/paper-reading/paper-reading-note-2</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-2/"><![CDATA[<p>This paper reading note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/81865049025">CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Paper Reading" /><category term="Paper Reading" /><category term="CXL" /><category term="Disaggregated Memory" /><summary type="html"><![CDATA[A paper reading note on CXL-DMSim, a full-system CXL disaggregated-memory simulator with silicon validation.]]></summary></entry><entry><title type="html">A Short Analysis of Transformer Acceleration</title><link href="https://xiangui33423.github.io/yaowentao/blog/thoughts/transformer-acceleration-analysis/" rel="alternate" type="text/html" title="A Short Analysis of Transformer Acceleration" /><published>2025-03-29T00:00:00+00:00</published><updated>2025-03-29T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/thoughts/transformer-acceleration-thought</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/thoughts/transformer-acceleration-analysis/"><![CDATA[<p>This short note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/1889273322287641657">A Short Analysis of Transformer Acceleration</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Notes" /><category term="Transformer" /><category term="AI Accelerator" /><category term="Computer Architecture" /><summary type="html"><![CDATA[A short note on Transformer acceleration and the system-design tradeoffs behind AI accelerators.]]></summary></entry><entry><title type="html">SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023</title><link href="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-3/" rel="alternate" type="text/html" title="SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023" /><published>2024-05-14T00:00:00+00:00</published><updated>2024-05-14T00:00:00+00:00</updated><id>https://xiangui33423.github.io/yaowentao/blog/paper-reading/paper-reading-note-3</id><content type="html" xml:base="https://xiangui33423.github.io/yaowentao/blog/paper-reading/note-3/"><![CDATA[<p>This paper reading note was originally published on Zhihu:</p>

<p><a href="https://zhuanlan.zhihu.com/p/697748535">SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023</a></p>]]></content><author><name>wentao yao</name><email>yaowentao1216@126.com</email></author><category term="Paper Reading" /><category term="Paper Reading" /><category term="GPU" /><category term="Cache" /><summary type="html"><![CDATA[A paper reading note on sharing-aware caching for multi-chip GPUs.]]></summary></entry></feed>