wentao yao

wentao yao

Computer system and architecture.

wentao yao

I am a first-year master’s student at the Institute of Computing Technology, Chinese Academy of Sciences, with joint training at Huawei. My graduate advisor is Prof. Ke Liu, and my Huawei mentor is Zixuan Guan.

My research interests are in computer systems and architecture, with a current focus on CXL memory pooling, memory congestion, next-generation interconnection systems, AI accelerators, computer networks, and LLM KVCache management and optimization.

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Selected Projects

LocWeave

Locality Isolation for CXL Memory Pooling

CXL memory pooling improves capacity and bandwidth sharing, but fine-grained interleaving can destroy memory locality by mixing incompatible requester streams inside shared memory devices. LocWeave explores pattern-aware placement and remapping mechanisms to reduce interference in multi-host CXL systems.

CXL Memory PoolingMemory CongestionMemory Systemsgem5DRAMSim3

HeteroSim

Memory-Space Design Exploration Simulator for Multi-Chiplet LLM Accelerators

HeteroSim is a simulator for exploring memory-space design choices in multi-chiplet LLM accelerators. It supports architectural studies of how heterogeneous memory organization, chiplet-level resource allocation, and accelerator data movement affect large-model inference and training efficiency.

LLM AcceleratorsMulti-Chiplet SystemsMemory Space DesignArchitecture Simulation

Mooncake Master Snapshot Refactoring

KVCache-Centric Serving System Snapshot Subsystem Refactor

Around Mooncake Store RFC #2688, I split master snapshot orchestration, repository operations, codec logic, and restore flow out of the monolithic MasterService through 4 merged PRs: #2805, #2831, #2879, and #2943. The refactor preserves the snapshot format, configuration, and external behavior while improving module boundaries, testability, and future format evolution.

MooncakeKVCache ServingSnapshot/RestoreC++System Refactoring

AI Coprocessor Accelerator for LLM Workloads

Transformer-Oriented Accelerator Design

This project designs an AI coprocessor accelerator for LLM-oriented Transformer workloads. It explores hardware support for efficient matrix computation, data movement, and memory access patterns in neural-network inference acceleration.

LLM AccelerationAI CoprocessorTransformerHardware Design

Programmable Switch Data-Plane Project

P4-Based Switch and Packet-Processing Design

This project explores switch behavior and packet-processing logic with P4-style programmable data planes. It focuses on building and experimenting with network forwarding functions in a programmable switch environment.

Programmable SwitchP4Data PlaneComputer Networks

Current Directions

  • Memory systems for CXL pooling: understanding congestion, interference, and resource placement in shared and disaggregated memory.
  • Accelerator architecture for LLMs: exploring chiplet-level memory organization, data movement, and AI coprocessor support for Transformer workloads.
  • Programmable networking: prototyping packet-processing and forwarding mechanisms with P4-style data planes.
  • LLM KVCache systems: studying KVCache transfer, management, and optimization, as well as distributed KVCache serving systems.

Open Source Contributions

I have contributed to the Mooncake open-source project. Mooncake is a KVCache-centric serving system for large language model inference, focusing on high-performance KV cache transfer and distributed KV cache management.

I have merged 6 Pull Requests into the main branch: #2691, #2754, #2805, #2831, #2879, and #2943. My earlier contributions focused on GPU device management in the Transfer Engine and correctness of multi-GPU NVLink/MNNVL communication.

Recently, I completed the Mooncake Store master snapshot subsystem refactor around RFC #2688, split across four merged PRs:

  • #2805: extracted MasterSnapshotManager and MasterSnapshotRepository, separating snapshot scheduling, child process lifecycle, and storage/catalog operations from MasterService.
  • #2831: extracted MasterSnapshotCodec to own master snapshot encode/decode logic and added codec unit tests.
  • #2879: refactored the snapshot restore path into a repository, codec, and service-apply three-phase architecture while preserving snapshot format and restore behavior compatibility.
  • #2943: removed leftover wrapper methods after the refactor and documented the three-phase restore architecture.