CXL Memory Interleaving and Address Mapping less than 1 minute read Published: January 29, 2026This short note was originally published on Zhihu:CXL Memory Interleaving and Address MappingDirect LinkShare on Bluesky Facebook LinkedIn Mastodon X (formerly Twitter) Previous Next
A Brief Survey of Memory Bank Parallelism Permalink less than 1 minute read Published: May 21, 2026A short survey note on Memory Bank Parallelism, covering the basic idea of bank-level parallelism and its performance impact in memory systems.
Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011 Permalink less than 1 minute read Published: December 30, 2025A paper reading note on application-aware memory channel partitioning for reducing memory interference in multicore systems.
Understanding Computer-System Performance Tradeoffs Through the Roofline Model Permalink less than 1 minute read Published: November 24, 2025A short note on using the Roofline model to reason about performance bottlenecks and design tradeoffs in computer systems.
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025 Permalink less than 1 minute read Published: October 22, 2025A paper reading note on CXL-DMSim, a full-system CXL disaggregated-memory simulator with silicon validation.