A Short Analysis of Transformer Acceleration Permalink
Published:
A short note on Transformer acceleration and the system-design tradeoffs behind AI accelerators.
Posts by Tags
AI Accelerator
Address Mapping
CXL Memory Interleaving and Address Mapping Permalink
Published:
A short note on CXL memory interleaving and the address-mapping mechanisms behind it.
CXL
CXL Memory Interleaving and Address Mapping Permalink
Published:
A short note on CXL memory interleaving and the address-mapping mechanisms behind it.
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025 Permalink
Published:
A paper reading note on CXL-DMSim, a full-system CXL disaggregated-memory simulator with silicon validation.
Cache
SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023 Permalink
Published:
A paper reading note on sharing-aware caching for multi-chip GPUs.
Computer Architecture
A Short Analysis of Transformer Acceleration Permalink
Published:
A short note on Transformer acceleration and the system-design tradeoffs behind AI accelerators.
Computer Systems
Understanding Computer-System Performance Tradeoffs Through the Roofline Model Permalink
Published:
A short note on using the Roofline model to reason about performance bottlenecks and design tradeoffs in computer systems.
DRAM
A Brief Survey of Memory Bank Parallelism Permalink
Published:
A short survey note on Memory Bank Parallelism, covering the basic idea of bank-level parallelism and its performance impact in memory systems.
Disaggregated Memory
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025 Permalink
Published:
A paper reading note on CXL-DMSim, a full-system CXL disaggregated-memory simulator with silicon validation.
GPU
SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023 Permalink
Published:
A paper reading note on sharing-aware caching for multi-chip GPUs.
Memory Bank Parallelism
A Brief Survey of Memory Bank Parallelism Permalink
Published:
A short survey note on Memory Bank Parallelism, covering the basic idea of bank-level parallelism and its performance impact in memory systems.
Memory Channel Partitioning
Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011 Permalink
Published:
A paper reading note on application-aware memory channel partitioning for reducing memory interference in multicore systems.
Memory Systems
A Brief Survey of Memory Bank Parallelism Permalink
Published:
A short survey note on Memory Bank Parallelism, covering the basic idea of bank-level parallelism and its performance impact in memory systems.
CXL Memory Interleaving and Address Mapping Permalink
Published:
A short note on CXL memory interleaving and the address-mapping mechanisms behind it.
Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011 Permalink
Published:
A paper reading note on application-aware memory channel partitioning for reducing memory interference in multicore systems.
Paper Reading
Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning, MICRO 2011 Permalink
Published:
A paper reading note on application-aware memory channel partitioning for reducing memory interference in multicore systems.
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation, TCAD 2025 Permalink
Published:
A paper reading note on CXL-DMSim, a full-system CXL disaggregated-memory simulator with silicon validation.
SAC: Sharing-Aware Caching in Multi-Chip GPUs, ISCA 2023 Permalink
Published:
A paper reading note on sharing-aware caching for multi-chip GPUs.
Performance Analysis
Understanding Computer-System Performance Tradeoffs Through the Roofline Model Permalink
Published:
A short note on using the Roofline model to reason about performance bottlenecks and design tradeoffs in computer systems.
Roofline
Understanding Computer-System Performance Tradeoffs Through the Roofline Model Permalink
Published:
A short note on using the Roofline model to reason about performance bottlenecks and design tradeoffs in computer systems.
Transformer
A Short Analysis of Transformer Acceleration Permalink
Published:
A short note on Transformer acceleration and the system-design tradeoffs behind AI accelerators.